In order to provide a check on the accuracy of an incoming code word and to facilitate the correction of errors, use is made in such data-transmission systems of binary code words of n-bits each which consist of a group of k information bits supplemented by (n-k) redundancy bits, all these bits constituting respective coefficients of a composite polynomial which normally is a multiple of a predetermined generator polynomial. The first k-bits, associated with the highest terms of the (n-1).sup.th --order polynomial, represent the information bits whereas the remaining (n-k) bits serve as a check. If the word is correctly received, division of the generator polynomial into the composite polynomial results in an integral quotient, with zero remainder. A detector circuit can thus decide whether the received word is to be delivered to a load for which it is intended, such as a message decoder, or whether an error signal is to be generated.
Such detector circuits are well known per se. Reference in this connection may also be made to commonly owned U.S. application Ser. No. 536,992, filed Dec. 27, 1974 by Gustavo Pavoni et al.
If the detected error is merely the result of faulty synchronization, i.e. a simple slip in the timing of the incoming signals causing the bit count to commence before the end of a preceding word or after the beginning of a succeeding one, corrective measures can be taken at the receiving end without the need for transmission of an error signal to the originating station. Such corrective measures may comprise a compensatory shift neutralizing the slip error.